(1) Field of the Invention
The present invention relates to a demodulator for digital modulation signals such as phase modulation and frequency modulation signals incorporated in a modem for digital data transmission through a cable or a radio system.
(2) Description of the Related Art
Demodulators for digital modulation signals such as phase modulation and frequency modulation signals including frequency detectors and integral discharge filters have the advantage over the demodulators including coherent detectors in reducing circuits.
FIG. 1 is a block diagram of a conventional demodulator for the digital modulation signals through MSK (Minimum Shift Keying) and QPSK (Quadrature Phase Shift keying).
The demodulator comprises a frequency detector 41, an integral discharge filter 42, and a decision device 43. The integral discharge filter 42 includes an integrator 44 and a discharge control circuit 45. The frequency detector 41 and integral discharge filter 42 constitute a phase detector which outputs phase deviation signals.
The frequency detector 41 outputs frequency detection signals to the integral discharge filter 42 upon receiving the digital modulation signals, and in turn, the integral discharge filter 42 outputs phase deviation signals to the decision device 43 which outputs demodulation data.
More precisely, having detected frequencies of the digital modulation signals, the frequency detector 41 outputs the frequency detection signals by means of the voltage depending on the deviation thereof to the integral discharge filter 42, which integrates the frequency detection signals for each time slot (transmission time per symbol), meaning that the integrator 44 discharges an electrical charge stored therein as a result of a preceding integration upon receiving a reset signal outputted every time slot from the discharge control circuit 45, and subsequently integrates the frequency detection signals for the following time slot. Thus, the integral discharge filter 42 serving as the phase detector with the frequency detector 41 outputs phase deviation signals to the decision device 43, which discriminates the polarity and/or magnitudes thereof using several thresholds in order to output demodulation data. The demodulator demodulates the frequency modulation signals by detecting the phase deviation based on the frequency modulation signals.
For the digital modulation signals through MSK, the decision device 43 outputs binary demodulation data by means of a voltage corresponding to 0 deviation as a threshold, because their carrier phase deviation is either +.pi./2 or -.pi./2. For the digital modulation signals through .pi./4-shift-QPSK, the decision device 43 outputs quaternary demodulation data by means of voltages corresponding to +.pi./2, 0, and -.pi./2 deviation as thresholds, because their carrier phase deviation is one of +3.pi./4, +.pi./4, -.pi./4, and -3.pi./4.
FIG. 2 shows a block diagram of a conceivable demodulator for digital modulation signals through GMSK (Gaussian Filtered Minimum Shift Keying) with large intersymbol interference due to Gaussian filters.
The demodulator comprises a frequency detector 51, an integral discharge filter 52, a subtracting device 53, a decision device 54, a shift register 55, and a generator 56 for interference signals from preceding data(hereinafter, simply referred to as the interference signals generator 56). The integral discharge filter 52 includes integrators 57 and 58 for 2-bit transmission time(hereinafter, simply referred to as the integrators 57 and 58), an integrator control circuit 59, and a switch 60.
The frequency detector 51 outputs frequency detection signals to the integral discharge filter 52 which outputs phase deviation signals to the subtracting device 53, and the subtracting device 53 subtracts therefrom interference signals from preceding data produced with the shift register 55 and interference signals generator 56, then outputs subtraction results to the decision device 54 which outputs demodulation data.
More precisely, having detected frequencies of digital modulation signals, the frequency detector 51 outputs the frequency detection signals by means of the voltage depending on the deviation thereof to the integral discharge filter 52, which integrates the frequency detection signals for each 2-bit transmission time, meaning that the each integrator 57 and 58 integrates the frequency detection signals for 2-bit transmission time by turns upon alternately receiving a reset signal outputted every 1-bit transmission time from the discharge control circuit 59. The switch 60 controlled by the discharge control circuit 59 switches back and forth, whereby the integral discharge filter 52 outputs phase deviation signals, or the frequency detection signals integrated for 2-bit transmission time, to the subtracting device 53.
Since the modulation signals through GMSK are affected by intersymbol interference caused by the filters of transmitters and receivers, the interference should be removed prior to the input into the decision device 54. For instance, phase deviation signals X.sub.n on the n'th transmission data S.sub.n can be expressed as follows:
{Form 1} EQU X.sub.n =A.times.S.sub.n-2 +B.times.S.sub.n-1 +B.times.S.sub.n +A.times.S.sub.n+1
Here, noise affection is not taken into consideration, and S.sub.n-2 and S.sub.n-1, and S.sub.n+1 represent the data preceding and succeeding to S.sub.n, respectively, and each data becomes either +1 or -1. Capital letters A and B represent constant values, such as corresponding values to .pi./8 and 3.pi./8 deviation, respectively, which indicate affection on S.sub.n from the preceding and succeeding data and are determined by modulation methods or filter characteristics.
The Generator 56 outputs the interference signals from preceding data expressed as A.times.S.sub.n-2 +B.times.S.sub.n-1 by means of the voltage depending on the interference to the subtracting device 53, which subtracts the interference signals from preceding data from the phase deviation signals X.sub.n, thereby outputting substantially interference-free signals X.sub.n ' expressed as B.times.S.sub.n +A.times.S.sub.n+1 to the decision device 54. The interference signals from the succeeding data A.times.S.sub.n+1 can not be removed from the signals X.sub.n' because S.sub.n+1 are unknown. Subsequently, the decision device 54 discriminates the polarity and/or magnitudes thereof using a given threshold in order to output demodulation data to outer apparatuses as well as to the shift register 55, which shifts the demodulation data to a bit clock maintaining them for 2-bit transmission time, thereby outputting S.sub.n-2 and S.sub.n-1 to the interference signals generator 56, enabling it to produce the interference signals A.times.S.sub.n-2 +B.times.S.sub.n-1.
However, the demodulators described as above do not circumvent the problem of phase lags due to the noise in the digital modulation signals such as a heat noise and a cross talk, which affect the precise operation of decision device 43 and 54, therefore increasing BER (bit error rate) thereof.
In those demodulators, the phase deviation signals X.sub.k of the k'th transmission data include a phase noise a.sub.k expressed as follows:
{Form 2} EQU a.sub.k =e.sub.k -e.sub.k-1
Here, e.sub.k refers to a phase noise element causing a phase lag between an ideal phase on the k'th transmission data and phase deviation signals X.sub.k, while e.sub.k-1 refers to a phase noise element by a phase lag between an ideal phase on the preceding transmission data, or the k-1'th transmission data, and preceding phase deviation signals X.sub.k-1 outputted either from the integral discharge filter 42, and in the integral discharge filter 52, e.sub.k-1 refers to a phase noise element by a phase lag between an ideal phase on the preceding transmission data, or the k-2'th transmission data, and preceding phase deviation signals X.sub.k-2.
Demodulators having coherent detectors have a phase noise consisting of e.sub.k only, while demodulators having the frequency detectors and integral discharge filters have a synthesized phase noise consisting of e.sub.k and e.sub.k-1, therefore retaining higher BER.